The present disclosure relates generally to circuit boards, lead frames, semiconductor devices, and methods for fabricating these components and, in particular, to a fine-pitch multi-terminal semiconductor device and a method for fabricating the same.
With miniaturization of semiconductor elements and increase in the number of terminals, the electrode pitch has become finer and finer. However, the electrode pitch of a board on which a semiconductor element is mounted cannot be reduced to the same degree as the reduction in the electrode pitch of the semiconductor element. Accordingly, it is necessary to increase the length of wires drawn from the semiconductor element in order to catch up with the reduction in the electrode pitch.
In addition, semiconductor devices are required of further miniaturization and cost reduction, and thus the electrode pitch of semiconductor elements tends to be further reduced. However, increase in the length of wires drawn from the semiconductor elements could promote wire sweep during injection of molding resin, thus possibly causing a short-circuit between adjacent wires. Therefore, increase in the wire length for catching up with the reduction of pitch has a limitation.
On the other hand, a method in which a sensor chip is mounted on a circuit chip as described below is known (see, for example, Japanese Laid-Open Patent Publication No. 2000-227439). In this method, a circuit chip on which electrodes are arranged around a chip mounting region is prepared. A sensor chip is then mounted on the chip mounting region, and electrodes of the sensor chip and the electrodes of the circuit chip are connected to each other by wire bonding. The electrodes around the chip mounting region are connected to electrodes provided on the outer periphery of the circuit chip which are connected to a package by wires.
Application of this method may lead to reduction in the length of wires drawn from a semiconductor element. Specifically, an interposer element including first electrodes provided around a mounting region for a semiconductor element and second electrodes provided on its outer periphery is prepared. In the interposer element, the first electrodes are respectively connected to associated ones of the second electrodes. The first electrodes of the interposer element are connected to electrodes of the semiconductor element mounted on the mounting region of the interposer element. The second electrodes of the interposer element are connected to electrodes of a circuit board. This structure is expected to reduce the wire length even in a case where a finer-pitch semiconductor element is mounted on a circuit board. In addition, it is also expected that such short wires reduce the wire diameter and, accordingly, the pad size. As a result, not only miniaturization but also cost reduction is expected.